Non-volatile memory integrated circuit chips are well known in the art. See for example U.S. Pat. Nos. 5,029,130 and 6,151,248. One form of a non-volatile memory integrated circuit chip is a “NAND” flash memory device in which a string of serially connected non-volatile memory cells are grouped in a NAND flash memory structure.
Referring to FIG. 1A there is shown a cross-sectional view of a prior art split gate NAND flash memory structure 10. (See “Split-Gate NAND Flash Memory At 120 nm Technology Node Featuring Fast Programming and Erase” by C. Y. Shu et al, 2004 symposium on VLSI Technology Digest of Technical Papers, p. 78–79). The NAND flash memory structure 10 is formed on a semiconductor substrate 12 of a first conductivity type. The NAND flash memory structure 10 has a first region 14 of a second conductivity type and a second region 16 of the second conductivity type in the substrate 12. The first region 14 and the second region 16 are spaced apart from one another to define a continuous channel region between the first region 14 and the second region 16. A plurality of floating gates (18A . . . 18N) are spaced apart from one another with each floating gate 18 positioned over a separate portion of the channel region and separated and insulated therefrom. The structure 10 further has a select gate 20 associated with each floating gate 18. The select gate 20 is positioned over another portion of the channel region, and is immediately adjacent to the associated floating gate 18 and is insulated therefrom. Finally, the structure 10 has a plurality of control gates 22 with each control gate 22 associated with a floating gate 18 and forming a stacked gate configuration with the associated floating gate 18.
Typically, the NAND gate structure 10 is formed in a column direction with the select gate 20 and the control gate 22 connecting the respective select gates and control gates in a row direction. A plan view of an array of such NAND structures 10 is shown in FIG. 1B.
The problem with the NAND structure 10 of the prior art is that it requires two row lines for each cell: one for the select gate 20 and one for the control gate 22. With two lines for each cell and where for non-volatile memory cells the lines must carry high voltages, there would be too many high voltage control lines required for the pitch of each cell. In addition, the NAND structure 10 is uni-directional in operation.
Memory arrays in which the adjacent rows/columns are electrically connected at ends of the array are well known. See, e.g. U.S. Pat. No. 6,825,084 (FIG. 2). Finally, control gates that are substantially T shaped positioned between a pair of floating gates and having a portion over a channel region, and capacitively coupled to the pair of floating gates is also well known in the art. See e.g. U.S. Pat. No. 6,151,248.
Accordingly, there is a need to reduce the line count per cell to thereby improve the pitch of the nonvolatile memory device.